VIP
Feature
- PC16550D/PC16650D UART with FIFOs
- Configurable Baud Rate Divisor
- Configurable Fractional Baud Rate Divisor
- Configurable data width with 9 bits as well as 5-8 bits
- Line Break generation and detection - ?
- Hardware/Out-band Flow Control - ?
- Software/In-band Flow Control - ?
- Programmable 1 and 2 stop bits
- Programmable Parity(even/odd/stick/no-parity)
- Receiver FIFO(configurable depth)
- Configurable sample rate
- Programmable baud generator is implemented, which divides any input clock by 1 to (2*16 - 1) ad generates 16x clock
- Full duplex operation
- UVM
- DTE or DCE agent - ?
- protocol checks - ?
- callbacks - ?
- exceptions
- seq collection
- functional coverage
- verif planner
- source code
- debug
- quick start
- html
- user guide
Architecture overview