UVM

1. What is UVM? What is the advantage of UVM?

Ans: UVM(Universal Verification Methodology) is a standardized methodology for verifying both complex & simple digital design in simple way.

2. UVM Derived from which language?

Ans: From OVM(Open Vericication Methodology) and VMM(Verification Methodology Manual)

3. What is the difference between uvm_component and uvm_object? OR We already have uvm_object, why do we need uvm_component which is actually derived class of uvm_object?

Ans:

uvm_component

Quasi Static Entity(after build phase it is available throughout the simulation)
Always tied to a given hardware(DUT interface) or a TLM port
Having phasing mechanism for control the behavior of simulation
Configuration Component Topology

uvm_object

Dynamic Entity(create when needed, trnasfer from one component to other & then dereference)
Not tied to a given hardware or any TLM port
Not phasing mechanism

4. Why phasing is used? What are the different phases in uvm?

Ans: UVM Phases is used to control the behavior of simulation in a systematic way & execute in a sequential ordered to avoid race condition. This could also be done in system verilog but manually.

List of UVM Phases:

Build Phase
Connect Phase
End of elaboration Phase
Start of simulation Phase
Run Phase:
- Pre-Reset-Post Phase
- Pre-Configure-Post Phase
- Pre-Main-Post Phase
- Pre-Shutdown-Post Phase
extract Phase
Check Phase
Report Phase

5. Which uvm phase is top-down, bottom-up & parallel?

Ans: Only build phase is a top-down & other phases are bottom -up except run phase which is parallel. The build phase works top-down since the testbench hierarchy may be configure so we need to build the branches before leafs.

6. Why build phase is top-down & connect phase is bottom-up?

Ans: The connect phase is intended to be used for making TLM connections between components, which is why it occur after build phase. It work bottom-up so that its got the correct implementation all the way up the design hierarchy. If worded top-down this would be not possible.

7. Which phase is function & which phase is task?

Ans: Only run phase is task(time consuming phase) & other pahses are functions(non-blocking)

8. How uvm phases initiate?

Ans: UVM phases initiate by calling run_test() in top module. The Method run_test() first creates the object of test top & then calls all phases.

9. How test cases run from simulation command line?

Ans: In top module write run_test(); then in command line: +UVM_TESTNAME=testname

10. Difference between module & class based TB?

Ans: A module is a static object present always during the simulation. A Class is a dynamic object because they can come and go during the life time of simulation.

11. What is uvm_config_db? What is difference between uvm_config_db & uvm_resource_db?

Ans: uvm_config_db is a parameterized class used for configuration of different type of parameter into the uvm database, so that it can be used by any component in the lower level of hierarchy.

uvm_config_db is a convenience layer built on top of uvm_resource_db, but that convenience is very important. In particular, uvm_resource_db uses a "last write wins" approach. The uvm_config_db, on the other hand, looks at where things are in the hierarchy up through end_of_elaboration, so "parent wins." Once you start start_of_simulation, the config_db becomes "last write wins."

All of the functions in uvm_config_db#(T) are static, so they must be called using the :: operator It is extended from the uvm_resource_db#(T), so it is child class of uvm_resource_db#(T

12.

I asked him basic question on System Verilog data structures (queue/associative array) and he was clearly unfamiliar. The same for Constraint/Coverage. Then in UVM, he has probably coded tests and changed sequences but he doesn’t know the details such as how an interface is passed to a driver, what is a virtual sequencer, etc.

UVM

UVM